Memory controller


PURPOSE: To start simultaneously memories of plural banks by providing a means by which each main memory starts the operation in accordance with a memory start request in case of the block transfer mode through its own bank is not selected. CONSTITUTION: The data transfer request from a CPU 100 is received first by a cache memory 300. In case of read hit, data is read from the cache memory 300; but in case of read miss, data is read from a main memory 400 and is sent back to the transfer request source, and one-block components of data in the cache memory 300 are read and are written in the cache memory 300. In case of write hit, data is written in the cache memory 300 and the main memory 400; but in case of write miss, data is written in only the main memory 400. COPYRIGHT: (C)1987,JPO&Japio




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